The VHDL module "fifo" (see symbol) stores data based on the "first in, first out" principle.
The module "fifo" implements the "First-Word-Fall-Through" read operation (FWFT),
this means the first word appears at its output without any read operation.
As the module "fifo" stores the data in a synchronous RAM, the FWFT feature causes a
more complex control logic compared to a flipflop based implementation.
The module is configurable by generics in order
The module "fifo" was developed with HDL-SCHEM-Editor.
| Port name | Direction | Description |
|---|---|---|
| res_i | input | asynchronous reset input, 1-active |
| clk_i | input | clock input |
| data_i(g_data_width-1:0) | input | Data to be stored in the Fifo. |
| write_fifo_i | input | An 1-active impulse of 1 clock cycle will store the value at data_i in the Fifo. After the clock edge the value at data_i shows up at data_o without any read operation. |
| read_fifo_i | input | An 1-active impulse of 1 clock cycle will read the next data from the Fifo. This next data shows up at data_o after the clock edge. |
| fifo_empty_o | output | Is at 1 as long as no data is stored in the Fifo. |
| last_o | output | Is at 1 as long only one data is stored in the Fifo. |
| fifo_fill_o | output | Is at 1 as long as the Fifo is full. |
| data_o(g_data_width-1:0) | output | Here always the "first out" value is visible. After a clock cycle with read_fifo_i=1, the next value shows up. |
| fifo_overflow_o | output | Is a 1-active impulse of one clock period, when write_fifo_i was active in a clock cycle where fifo_full_o was 1. |
| fifo_underflow_o | output | Is a 1-active impulse of one clock period, when read_fifo_i was active in a clock cycle where fifo_empty_o was 1. |
| Generic name | Minimum Value | Maximum Value | Description |
|---|---|---|---|
| g_fifo_depth | 1 | n/a | The maximum number data words which can be stored in the Fifo. As the Fifo is implemented by a RAM it is a good idea to set g_fifo_depth to a power of 2, because in this case the RAM is completely used and no RAM word is wasted. |
| g_data_width | 1 | n/a | Number of bits of data_i and data_o. |
The module "fifo" is a hierarchical module, which is built by 3 submodules.
| Submodule name | Functionality |
|---|---|
| fifo_control |
This submodule is a state machine which controls the ring buffer in the RAM (used to implement the Fifo). It also creates all the status outputs (fifo_empty_o, last_o, fifo_fill_o, fifo_overflow_o, fifo_underflow_o). |
| fifo_ram |
This submodule implements a simple synchronous RAM (as it is available in many FPGAs). |
| fifo_data_reg |
This submodule stores the "first out"-value.
It is needed to provide the "first out" value at data_o immediately after the first write and |
Source code for HDL-SCHEM-Editor and HDL-FSM-Editor for module "fifo" and its testbenches (Number of downloads =
17 ).
With these files the schematics and the state-diagram can be loaded into HDL-SCHEM-Editor or HDL-FSM-Editor and can be easily read and modified:
All module VHDL-files of the module "fifo" (Number of downloads =
18 ).
These files were generated by HDL-SCHEM-Editor and HDL-FSM-Editor:
All testbench VHDL-files of the 2 testbenches of the module "fifo" (Number of downloads =
19 ).
These files were generated by HDL-SCHEM-Editor and HDL-FSM-Editor:
You should extract all archives into a folder named "fifo".
Then you should load the toplevel (probably the testbench) into HDL-SCHEM-Editor.
When you navigate through the design hierarchy by a double click at each symbol,
HDL-SCHEM-Editor will find the submodules on your disk and ask if it can replace
the original path to the submodule by the new one at your disk.
After storing the changed modules the relocation of the source files is ready
(instead you could replace "M:/gesicherte Daten/Programmieren/VHDL/fifo" in all
"hdl_editor_designs/*.hse" source files by your path to this directory with your editor).
Now you can navigate through the design by HDL-SCHEM-Editor and generate HDL by HDL-SCHEM-Editor for
all modules except fifo_control, for which the HDL must be generated by HDL-FSM-Editor.
Of course there is only need for generating HDL, if you change something at the modules, because you can find the HDL in VHDL_designs.zip and VHDL_testbenches.zip.
If you want to simulate or modify the modules by HDL-SCHEM-Editor you also must adapt the information in the Control-tab of the toplevel you want to work on.
There you must define a "Compile through hierarchy command", an "Edit command", the path to your HDL-FSM-Editor and a "Working directory".
Version 1.0 (28.03.2025):
If you detect any bugs or have any questions,
please send a mail to "matthias.schweikart@gmx.de".