The VHDL 2008 module "axi_ahb_bridge" (see symbol)
connects an AXI4 master interface to an AHB-Lite slave interface.
The axi_ahb_bridge complies with the AMBA® AXI Protocol Specification (ARM IHI 0022 Issue L).
The axi_ahb_bridge implements the AXI4 protocol (not supporting QoS signaling, Multiple-region-, User-defined- signaling).
The axi_ahb_bridge complies with the AMBA® AHB Protocol Specification (ARM IHI 0033C).
The axi_ahb_bridge implements the AHB-Lite protocol, named "Issue A" in the specification.
The axi_ahb_bridge module is configured by generics, which determine the width of address and data buses.
Any burst initiated at the AXI side must not cross a 1 kB address, as this is a AHB restriction.
Unaligned AXI transactions are transformed into aligned accesses at AHB.
Unaligned AXI transactions use WSTRB signals, which are used as HWSTRB signals without any change.
AXI FIXED bursts are executed as AHB SINGLE transfers (as the address is not changing).
An AXI WRAP with length 2 is executed as 2 AHB SINGLE transfers (as no wrap2 exists at AHB).
Exclusive AXI transactions are executed as locked transfers at AHB (hmastlock=1).
When an exclusive write access must be suppressed, then this is done by deasserting HWSTRB signals.
An AXI write transfer is detected as soon as the AW transfer and the first corresponding W transfer are done.
When an AXI write transaction and an AXI read transaction are detected at the same time, and the last AHB
transfer was a read, then the AXI write is executed first, otherwise the AXI read is executed first.
So neither read nor write transactions can occupy the AHB permanentely.
In order to support single accesses without any gap at AXI, there is an additional transfer buffer
implemented for AR-, AW- and W-channel (without these buffers a combinatorial path from hready_i
to arready_o, awready_o, wready_o would have been necessary to make accesses without gap possible).
Therefore the axi_ahb_bridge accepts 2 transfers at AR-, AW- or W-channel, before ARREADY, AWREADY or WREADY is deactivated.
When permanentely ARLEN=0, RREADY=1, HREADY=1 then accesses without any gap at AR-, R-channel and AHB are performed.
When permanentely AWLEN=0, BREADY=1, HREADY=1 then accesses without any gap at AW-, B-channel and AHB are performed.
A next write transaction is earliest started at AHB as soon as the B-channel accepts the transfer of the current last response.
A next read transaction is earliest started at AHB as soon as the R-channel accepts the transfer of the last read response.
When read data at the R-channel is available but not picked up or when write data at W-channel is not available but needed,
then IDLE (at FIXED) or BUSY (at not FIXED) is used for waiting at AHB.
The fastest read and the fastest write transaction needs only 3 clock cycles.
Responses at R and B-channel are limited to OKAY, EXOKAY, SLVERR.
The "axi_ahb_bridge" module was developed with HDL-SCHEM-Editor.
| Port name | Direction | Description |
|---|---|---|
| aresetn_i | input | asynchronous reset input, 0-active |
| aclk_i | input | clock input |
| ar_i | input | This input is a record containing the following AXI signals: araddr(g_addr_width-1:0), arlen(7:0), arsize(2:0), arburst(1:0), arlock, arcache(3:0), arprot(2:0), arid(3:0), arvalid. |
| arready_o | output | ready signal for AR channel. |
| aw_i | input | This input is a record containing the following AXI signals: awaddr(g_addr_width-1:0), awlen(7:0), awsize(2:0), awburst(1:0), awlock, awcache(3:0), awprot(2:0), awid(3:0), awvalid. |
| awready_o | output | ready signal for AW channel. |
| w_i | input | This input is a record containing the following AXI signals: wdata(g_data_width-1:0), wstrb(g_data_width/8-1:0), wlast, wvalid. |
| wready_o | output | ready signal for W channel. |
| r_o | output | This output is a record containing the following AXI signals: rdata(g_data_width-1:0), rresp(1:0), rid(3:0), rlast, rvalid. |
| rready_i | input | ready signal for R channel. |
| b_o | output | This output is a record containing the following AXI signals: bresp(1:0), bid(3:0), bvalid. |
| bready_i | input | ready signal for B channel. |
| hcontrol_o | output | This output is a record containing the following AHB signals: htrans(1:0), haddr(g_addr_width-1:0), hwrite, hsize(2:0), hburst(g_hburst_width-1:0), hprot(g_hprot_width-1:0), hmastlock. |
| hwdata_o(g_data_width-1:0) | output | AHB write data bus. |
| hwstrb_o(g_data_width/8-1:0) | output | AHB write strobe signals. |
| hready_i | input | AHB ready signal. |
| hrdata_i(g_data_width-1:0) | input | AHB read data bus. |
| hresp_i | input | AHB error response. |
| Generic name | Minimum Value | Maximum Value | Description |
|---|---|---|---|
| g_addr_width | 8 | n/a | Width of the addresses. The AXI Protocol Specification allows values between 1 and 64. The AHB Protocol Specification recommends values between 10 and 64. |
| g_data_width | 8 | 1024 | Width of the data busses The AXI and the AHB Specification allows the values 8, 16, 32, 64, 128, 256, 512, 1024. |
| g_hburst_width | 3 | 3 | Width of hburst (contained in hcontrol_o). Allowed values from AHB Protocol Specification are 0 or 3. |
| g_hprot_width | 4 | 7 | Width of hprot (contained in hcontrol_o). Allowed values from AHB Protocol Specification are 0, 4 or 7. |
The module "axi_ahb_bridge" is a hierarchical module, which is built by 8 submodules.
| Submodule name | Functionality |
|---|---|
| ahb_package |
The package ahb_package contains several type definitions. Some of them use VHDL 2008 unconstrained array types. This is the only used VHDL 2008 feature in the "axi_ahb_bridge" module. There is also a "or" function included for combining hcontrol signals and a debug procedure, which can be used to look inside the signals of record-type t_ahb_control, if your waveform viewer does not support records. |
| axi_package |
The package axi_package contains several type definitions. Some of them use VHDL 2008 unconstrained array types. This is the only used VHDL 2008 feature in the "axi_ahb_bridge" module. |
| axi_ahb_bridge_axi_slave_a |
The "axi_ahb_bridge_axi_slave_a" submodule is used twice and handles the AXI AR-channel and the AXI AW-channel. |
| axi_ahb_bridge_axi_slave_w |
The "axi_ahb_bridge_axi_slave_w" submodule handles the AXI W-channel |
| axi_ahb_bridge_axi_master_r |
The "axi_ahb_bridge_axi_master_r" submodule handles the AXI R-channel |
| axi_ahb_bridge_axi_master_b |
The "axi_ahb_bridge_axi_master_b" submodule handles the AXI B-channel |
| axi_ahb_bridge_arbiter |
The "axi_ahb_bridge_arbiter" submodule decides whether a read transaction or a write transaction has higher priority. |
| axi_ahb_bridge_ahb_master |
The "axi_ahb_bridge_ahb_master" submodule handles the AHB bus. |
| axi_ahb_bridge_address_calculation |
The "axi_ahb_bridge_address_calculation" submodule calculates the addresses for the AHB transfers. |
| axi_ahb_bridge_ex_access_monitor |
The "axi_ahb_bridge_ex_access_monitor" submodule monitors the exclusive access transactions and is used 16 times. |
For an instance of the axi_ahb_bridge module the packages axi_package and ahb_package must be used to introduce the data types at axi_ahb_bridge's ports.
If this is not allowed or wished, then a shell around axi_ahb_bridge can help.
In this shell the conversion from the special axi_ahb_bridge data types to the standard data types can be realized.
There also the generics of the axi_ahb_bridge module can be set, so that the entity of the shell does not have special types or generics.
Source code for HDL-SCHEM-Editor and HDL-FSM-Editor for "axi_ahb_bridge" module and its testbench (Number of downloads =
8 ).
With these files the schematics and the state-diagram of "axi_ahb_bridge" module can be loaded into HDL-SCHEM-Editor or
HDL-FSM-Editor and can be easily read and modified:
All module VHDL-files of the "axi_ahb_bridge" module (Number of downloads =
14 ).
These files were generated by HDL-SCHEM-Editor and HDL-FSM-Editor:
All testbench VHDL-files of the "axi_ahb_bridge" module (Number of downloads =
7 ).
These files were generated by HDL-SCHEM-Editor and HDL-FSM-Editor:
You should extract all archives into a folder named "axi_ahb_bridge".
Then you should load the toplevel (probably the testbench) into HDL-SCHEM-Editor.
When you navigate through the design hierarchy by a double click at each symbol,
HDL-SCHEM-Editor will find the submodules on your disk and ask if it can replace
the original path to the submodule by the new one at your disk.
After storing the changed modules the relocation of the source files is done
(instead you could replace "M:/gesicherte Daten/Programmieren/VHDL/axi_ahb_bridge" in all
"hdl_editor_designs/*.hse" source files by your path to this directory with your editor).
Now you can navigate through the design by HDL-SCHEM-Editor and generate HDL by HDL-SCHEM-Editor
for all modules except axi_ahb_bridge_axi_slave_a, axi_ahb_bridge_axi_slave_w,
axi_ahb_bridge_axi_master_b, axi_ahb_bridge_axi_master_r and axi_ahb_bridge_ahb_master,
for which the HDL must be generated by HDL-FSM-Editor.
Of course there is only need for generating HDL, if you change something at the modules,
because you can find the HDL in VHDL_designs.zip and VHDL_testbenches.zip.
If you want to simulate or modify the modules by HDL-SCHEM-Editor you also must adapt the information in the
Control-tab of the toplevel you want to work on. There you must define a "Compile through hierarchy command",
an "Edit command", the path to your HDL-FSM-Editor and a "Working directory".
Version 1.0 (10.06.2026):
If you detect any bugs or have any questions,
please send a mail to "matthias.schweikart@gmx.de".