The VHDL 2008 module "ahb_apb_bridge" (see symbol) connects one AHB master to several APB slaves.
The "ahb_apb_bridge" complies with the AMBA® APB Protocol Specification (ARM IHI 0024E).
The "ahb_apb_bridge" implements the AMBA APB Specification APB4, named "Issue C".
The "ahb_apb_bridge" module is configured by generics, which determine the number of slaves,
the start addresses and address width of the slaves, the parameters of the AHB protocol specification,
the endianness and the address and data width.
The "ahb_apb_bridge" has a AHB slave interface and several APB master interfaces.
The "ahb_apb_bridge" introduces a 1 clock cycle delay to the first of a sequence of accesses from master to slave,
because the APB protocol needs the write data, before an access can be started.
The "ahb_apb_bridge" module was developed with HDL-SCHEM-Editor.
| Port name | Direction | Description |
|---|---|---|
| presetn_i | input | asynchronous reset input, 0-active |
| pclk_i | input | clock input |
| hready_i | input | AHB ready signal (active in valid AHB address phase). |
| hsel_i | input | AHB select signal. |
| hcontrol_i | input | This input is a record containing the following AHB signals: htrans, haddr, hwrite, hsize, hburst, hprot, hmastlock. |
| hwdata_i(g_data_width-1:0) | input | AHB write data bus. |
| hreadyout_o | output | AHB slave ready signal. |
| hrdata_o(g_data_width-1:0) | output | AHB read data bus. |
| hresp_o | output | AHB error response. |
| psel_o(g_number_of_apb_slaves-1:0) | output | APB select signal for each slave. |
| penable_o | output | APB enable signal. |
| pwrite_o | output | APB write signal. |
| pprot_o(2:0) | output | APB protection signal. |
| paddr_o(g_addr_width-1:0) | output | APB address bus. |
| pwdata_o(g_data_width-1:0) | output | APB write data bus. |
| pstrb_o(g_data_width/8-1:0) | output | APB byte enable signals. |
| pready_i(g_number_of_apb_slaves-1:0) | input | APB ready signal from each slave. |
| prdata_i(g_number_of_apb_slaves-1:0)(g_data_width-1:0) | input | APB read data from each slave. |
| pslverr_i(g_number_of_apb_slaves-1:0) | input | APB error response from each slave. |
| Generic name | Minimum Value | Maximum Value | Description |
|---|---|---|---|
| g_endianness | 1 | 2 | g_endianness==1: little endian or byte-invariant big-endian; g_endianness==2: word-invariant big-endian (see AMBA® APB Protocol Specification (ARM IHI 0024E), Issue C). All values different from 1 are interpreted as 2. |
| g_number_of_apb_slaves | 1 | none | Number of APB slaves |
| g_addr_width | n/a | n/a | Width of the address busses paddr_o and haddr (contained in hcontrol_i). The AHB Protocol Specification recommends values between 10 and 64. The selected value must be big enough to include the address spaces of all slaves. |
| g_data_width | 8 | 1024 | Width of the data busses hwdata_i, pwdata_o and prdata_i. The AHB Protocol Specification allows the values 8, 16, 32, 64, 128, 256, 512, 1024. The APB Protocol Specification allows the values 8, 16, 32, but bigger values are supported by "ahb_apb_bridge". |
| g_hburst_width | 0 | 3 | Width of hburst (contained in hcontrol_i). Allowed values from AHB Protocol Specification are 0 or 3. |
| g_hprot_width | 0 | 7 | Width of hprot (contained in hcontrol_i). Allowed values from AHB Protocol Specification are 0, 4 or 7. |
| g_apb_start_addresses | n/a | n/a | This is an array of std_logic_vector values, each entry representing the start address of the corresponding slave. |
| g_apb_slave_address_width | n/a | n/a | This is an array of integers, each entry representing the number of address bits the corresponding APB slave evaluates. |
The module "ahb_apb_bridge" is a hierarchical module, which is built by 2 submodules.
| Submodule name | Functionality |
|---|---|
| ahb_package |
The package ahb_package contains several type definitions. Some of them use VHDL 2008 unconstrained array types. There is also a debug procedure included, which can be used to look inside the hcontrol signals (type record), if your waveform viewer does not support records. |
| ahb_apb_bridge_access_handler |
The "ahb_apb_bridge_access_handler" submodule detects AHB accesses and converts them into APB accesses. |
| ahb_apb_bridge_mux |
The "ahb_apb_bridge_mux" submodule is a multiplexer connecting the selected APB slave to the "ahb_apb_bridge_access_handler". |
The "ahb_apb_bridge" module must create select signals psel for the slaves depending on the hcontrol_i.haddr signal,
which is done in this way:
The start address of each slave is defined by the generic g_apb_start_addresses.
The number of address bits each slave observes is defined by the generic g_apb_slave_address_width.
This number of least significant bits is cut off from each slave start address and also from hcontrol_i.haddr.
The remaining address parts are compared for equality and the psel signals are generated.
In this way no address arithmetic is needed, which would make psel generation slow.
All needed multiplexers are implemented by setting the not selected inputs to 0 and then "oring" all inputs together.
As separate databusses exist for write and read data, ahb_apb_bridge never checks the status of the hcontrol_i.hwrite signal.
As a consequence at every write transfer the slave can deliver read data and at every read transfer the master can deliver write data.
This is used by the testbench components:
At each access, the hcontrol signals are copied into the write data at the master and
also the APB signals are copied into the read data at the slave.
This allows a lot of automatic checks at both master and slave side.
The testbench_ahb_apb_bridge supports only g_data_width values 32 and 64.
For an instance of the "ahb_apb_bridge" module the package "ahb_package" must be used to introduce the data types at "ahb_apb_bridge"'s ports.
If this is not allowed or wished, then a shell around "ahb_apb_bridge" can help.
In this shell the conversion from the special "ahb_apb_bridge" data types to the standard data types can be realized.
There also the generics of the "ahb_apb_bridge" module can be set, so that the entity of the shell does not have special types or generics.
Source code for HDL-SCHEM-Editor and HDL-FSM-Editor for "ahb_apb_bridge" module and its testbench (Number of downloads =
1 ).
With these files the schematics and the state-diagram of "ahb_apb_bridge" module can be loaded into HDL-SCHEM-Editor or
HDL-FSM-Editor and can be easily read and modified:
All module VHDL-files of the "ahb_apb_bridge" module (Number of downloads =
1 ).
These files were generated by HDL-SCHEM-Editor and HDL-FSM-Editor:
All testbench VHDL-files of the "ahb_apb_bridge" module (Number of downloads =
1 ).
These files were generated by HDL-SCHEM-Editor and HDL-FSM-Editor:
You should extract all archives into a folder named "ahb_apb_bridge".
Then you should load the toplevel (probably the testbench) into HDL-SCHEM-Editor.
When you navigate through the design hierarchy by a double click at each symbol,
HDL-SCHEM-Editor will find the submodules on your disk and ask if it can replace
the original path to the submodule by the new one at your disk.
After storing the changed modules the relocation of the source files is done
(instead you could replace "M:/gesicherte Daten/Programmieren/VHDL/ahb_apb_bridge" in all
"hdl_editor_designs/*.hse" source files by your path to this directory with your editor).
Now you can navigate through the design by HDL-SCHEM-Editor and generate HDL by HDL-SCHEM-Editor
for all modules except "ahb_apb_bridge_access_handler" for which the HDL must be generated by HDL-FSM-Editor.
Of course there is only need for generating HDL, if you change something at the modules,
because you can find the HDL in VHDL_designs.zip and VHDL_testbenches.zip.
If you want to simulate or modify the modules by HDL-SCHEM-Editor you also must adapt the information in the
Control-tab of the toplevel you want to work on. There you must define a "Compile through hierarchy command",
an "Edit command", the path to your HDL-FSM-Editor and a "Working directory".
Version 1.0 (03.12.2025):
If you detect any bugs or have any questions,
please send a mail to "matthias.schweikart@gmx.de".